1264 lines
40 KiB
C
1264 lines
40 KiB
C
/*
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* Copyright (c) 2020, Texas Instruments Incorporated
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* * Neither the name of Texas Instruments Incorporated nor the names of
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* its contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*!****************************************************************************
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* @file dl_aes.h
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* @brief Advanced Encryption Standard (AES) Driver Library
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* @defgroup AES Advanced Encryption Standard (AES)
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*
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* @anchor ti_dl_dl_aes_Overview
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* # Overview
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*
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* The AES DriverLib allows full configuration of the MSPM0 AES module.
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* The AES accelerator module accelerates encryption and decryption operations in hardware based
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* on the FIPS PUB 197 advanced encryption standard (AES).
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*
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* <hr>
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******************************************************************************/
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/** @addtogroup AES
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* @{
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*/
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#ifndef ti_dl_dl_aes__include
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#define ti_dl_dl_aes__include
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#include <stdbool.h>
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#include <stddef.h>
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#include <stdint.h>
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#include <ti/devices/msp/msp.h>
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#include <ti/driverlib/dl_common.h>
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#ifdef __MSPM0_HAS_AES__
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* clang-format off */
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/*!
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* @brief AES Ready interrupt
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*/
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#define DL_AES_INTERRUPT_AES_READY (AES_CPU_INT_IMASK_AESRDY_MASK)
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/*!
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* @brief DMA Trigger Event 0
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*/
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#define DL_AES_EVENT_AES_DMA_TRIGGER0 (AES_DMA_TRIG0_IMASK_DMA0_MASK)
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/*!
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* @brief DMA Trigger Event 1
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*/
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#define DL_AES_EVENT_AES_DMA_TRIGGER1 (AES_DMA_TRIG1_IMASK_DMA1_SET)
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/*!
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* @brief DMA Trigger Event 2
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*/
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#define DL_AES_EVENT_AES_DMA_TRIGGER2 (AES_DMA_TRIG2_IMASK_DMA2_SET)
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/* clang-format on */
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/*! @enum DL_AES_MODE */
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typedef enum {
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/*! @brief Selects encryption using Electronic Code Book (ECB) mode. */
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DL_AES_MODE_ENCRYPT_ECB_MODE =
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(AES_AESACTL0_OPX_OP0 | AES_AESACTL0_CMX_ECB),
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/*! @brief Selects encryption using Cipher Block Chaining (CBC) mode. */
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DL_AES_MODE_ENCRYPT_CBC_MODE =
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(AES_AESACTL0_OPX_OP0 | AES_AESACTL0_CMX_CBC),
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/*! @brief Selects encryption using Output Feedback (OFB) mode. */
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DL_AES_MODE_ENCRYPT_OFB_MODE =
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(AES_AESACTL0_OPX_OP0 | AES_AESACTL0_CMX_OFB),
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/*! @brief Selects encryption using Cipher Feedback (CFB) mode. */
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DL_AES_MODE_ENCRYPT_CFB_MODE =
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(AES_AESACTL0_OPX_OP0 | AES_AESACTL0_CMX_CFB),
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/*! @brief Selects decryption using Electronic Code Book (ECB) mode. */
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DL_AES_MODE_DECRYPT_SAME_KEY_ECB_MODE =
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(AES_AESACTL0_OPX_OP1 | AES_AESACTL0_CMX_ECB),
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/*! @brief Selects decryption using Cipher Block Chaining (CBC) mode. */
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DL_AES_MODE_DECRYPT_SAME_KEY_CBC_MODE =
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(AES_AESACTL0_OPX_OP1 | AES_AESACTL0_CMX_CBC),
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/*! @brief Selects decryption using Output Feedback (OFB) mode. */
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DL_AES_MODE_DECRYPT_SAME_KEY_OFB_MODE =
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(AES_AESACTL0_OPX_OP1 | AES_AESACTL0_CMX_OFB),
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/*! @brief Selects decryption using Cipher Feedback (CFB) mode. */
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DL_AES_MODE_DECRYPT_SAME_KEY_CFB_MODE =
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(AES_AESACTL0_OPX_OP1 | AES_AESACTL0_CMX_CFB),
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/*! @brief Selects first round key for Electronic Code Book (ECB) mode. */
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DL_AES_MODE_GEN_FIRST_ROUND_KEY_ECB_MODE =
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(AES_AESACTL0_OPX_OP2 | AES_AESACTL0_CMX_ECB),
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/*! @brief Selects first round key using Cipher Block Chaining (CBC) mode. */
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DL_AES_MODE_GEN_FIRST_ROUND_KEY_CBC_MODE =
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(AES_AESACTL0_OPX_OP2 | AES_AESACTL0_CMX_CBC),
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/*! @brief Selects first round key using Output Feedback (OFB) mode. */
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DL_AES_MODE_GEN_FIRST_ROUND_KEY_OFB_MODE =
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(AES_AESACTL0_OPX_OP2 | AES_AESACTL0_CMX_OFB),
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/*! @brief Selects first round key using Cipher Feedback (CFB) mode. */
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DL_AES_MODE_GEN_FIRST_ROUND_KEY_CFB_MODE =
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(AES_AESACTL0_OPX_OP2 | AES_AESACTL0_CMX_CFB),
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/*! @brief Selects decryption with 1st round key using ECB mode. */
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DL_AES_MODE_DECRYPT_KEY_IS_FIRST_ROUND_KEY_ECB_MODE =
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(AES_AESACTL0_OPX_OP3 | AES_AESACTL0_CMX_ECB),
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/*! @brief Selects decryption with 1st round key using CBC mode. */
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DL_AES_MODE_DECRYPT_KEY_IS_FIRST_ROUND_KEY_CBC_MODE =
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(AES_AESACTL0_OPX_OP3 | AES_AESACTL0_CMX_CBC),
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/*! @brief Selects decryption with 1st round key using OFB mode. */
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DL_AES_MODE_DECRYPT_KEY_IS_FIRST_ROUND_KEY_OFB_MODE =
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(AES_AESACTL0_OPX_OP3 | AES_AESACTL0_CMX_OFB),
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/*! @brief Selects decryption with 1st round key using CFB mode. */
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DL_AES_MODE_DECRYPT_KEY_IS_FIRST_ROUND_KEY_CFB_MODE =
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(AES_AESACTL0_OPX_OP3 | AES_AESACTL0_CMX_CFB),
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} DL_AES_MODE;
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/*! @enum DL_AES_IIDX */
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typedef enum {
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/*! AES interrupt index for AES module ready */
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DL_AES_IIDX_AES_READY = AES_CPU_INT_IIDX_STAT_AESRDY,
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/*! AES interrupt index for enabling DMA trigger event 0 */
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DL_AES_IIDX_AES_DMA_TRIGGER0 = AES_DMA_TRIG0_IIDX_STAT_DMA0,
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/*! AES interrupt index for enabling DMA trigger event 1 */
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DL_AES_IIDX_AES_DMA_TRIGGER1 = AES_DMA_TRIG1_IIDX_STAT_DMA1,
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/*! AES interrupt index for enabling DMA trigger event 2 */
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DL_AES_IIDX_AES_DMA_TRIGGER2 = AES_DMA_TRIG2_IIDX_STAT_DMA2
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} DL_AES_IIDX;
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/*! @enum DL_AES_OPERATION */
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typedef enum {
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/*! Encryption mode selected */
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DL_AES_OPERATION_ENC = AES_AESACTL0_OPX_OP0,
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/*! Decryption. The provided key is the same key used for encryption. */
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DL_AES_OPERATION_DEC_SAME_KEY = AES_AESACTL0_OPX_OP1,
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/*! Generate first round key required for decryption. */
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DL_AES_OPERATION_GEN_FIRST_ROUND = AES_AESACTL0_OPX_OP2,
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/*! Decryption. The provided key is the first round key required for
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* decryption */
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DL_AES_OPERATION_DEC_KEY_IS_FIRST_ROUND = AES_AESACTL0_OPX_OP3,
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} DL_AES_OPERATION;
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/*! @enum DL_AES_KEY_LENGTH */
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typedef enum {
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/*! Key length set to 128 */
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DL_AES_KEY_LENGTH_128 = AES_AESACTL0_KLX_AES128,
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/*! Key length set to 256 */
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DL_AES_KEY_LENGTH_256 = AES_AESACTL0_KLX_AES256,
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} DL_AES_KEY_LENGTH;
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/*! @enum DL_AES_STATUS */
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typedef enum {
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/*! Operation was successful */
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DL_AES_STATUS_SUCCESS,
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/*! Operation was not performed because address was unaligned */
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DL_AES_STATUS_UNALIGNED_ACCESS,
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} DL_AES_STATUS;
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/**
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* @brief Configuration structure to backup AES peripheral state before going
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* to STOP/STANDBY mode. Used by @ref DL_AES_saveConfiguration
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*/
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typedef struct {
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/*! Combination of AESACTL0 fields, compressed to a single word as they
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* are stored in the AES registers. See @ref DL_AES_init for
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* how the peripheral control word 0 is created */
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uint32_t controlWord0;
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/*! Combination of AESACTL1 fields, compressed to a single word as they
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* are stored in the AES registers. See @ref DL_AES_init for
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* how the peripheral control word 1 is created */
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uint32_t controlWord1;
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/*! AES interrupt mask 0. Value of @ref DL_AES_INTERRUPT_AES_READY stored
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* from the current state of the AES Interrupt Event 0 register set */
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uint32_t interruptMask0;
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/*! AES interrupt mask 1. Value of @ref DL_AES_EVENT_AES_DMA_TRIGGER0 stored
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* from the current state of the AES Interrupt Event 1 register set */
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uint32_t interruptMask1;
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/*! AES interrupt mask 2. Value of @ref DL_AES_EVENT_AES_DMA_TRIGGER1 stored
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* from the current state of the AES Interrupt Event 2 register set */
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uint32_t interruptMask2;
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/*! AES interrupt mask 3. Value of @ref DL_AES_EVENT_AES_DMA_TRIGGER2 stored
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* from the current state of the AES Interrupt Event 3 register set */
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uint32_t interruptMask3;
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/*! Boolean flag indicating whether or not a valid configuration structure
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exists. Should not be modified by the user. */
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bool backupRdy;
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} DL_AES_backupConfig;
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/**
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* @brief Enables the Peripheral Write Enable (PWREN) register for the AES
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*
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* Before any peripheral registers can be configured by software, the
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* peripheral itself must be enabled by writing the ENABLE bit together with
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* the appropriate KEY value to the peripheral's PWREN register.
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*
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* @param aes Pointer to the register overlay for the peripheral
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*/
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__STATIC_INLINE void DL_AES_enablePower(AES_Regs *aes)
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{
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aes->GPRCM.PWREN = (AES_PWREN_KEY_UNLOCK_W | AES_PWREN_ENABLE_ENABLE);
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}
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/**
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* @brief Disables the Peripheral Write Enable (PWREN) register for the AES
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*
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* When the PWREN.ENABLE bit is cleared, the peripheral's registers are not
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* accessible for read/write operations.
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*
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* @param aes Pointer to the register overlay for the peripheral
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*/
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__STATIC_INLINE void DL_AES_disablePower(AES_Regs *aes)
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{
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aes->GPRCM.PWREN = (AES_PWREN_KEY_UNLOCK_W | AES_PWREN_ENABLE_DISABLE);
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}
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/**
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* @brief Returns if the Peripheral Write Enable (PWREN) register for the AES
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* is enabled
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*
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* Before any peripheral registers can be configured by software, the
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* peripheral itself must be enabled by writing the ENABLE bit together with
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* the appropriate KEY value to the peripheral's PWREN register.
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*
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* When the PWREN.ENABLE bit is cleared, the peripheral's registers are not
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* accessible for read/write operations.
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*
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* @param aes Pointer to the register overlay for the peripheral
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*
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* @return true if peripheral register access is enabled
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* @return false if peripheral register access is disabled
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*/
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__STATIC_INLINE bool DL_AES_isPowerEnabled(const AES_Regs *aes)
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{
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return (
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(aes->GPRCM.PWREN & AES_PWREN_ENABLE_MASK) == AES_PWREN_ENABLE_ENABLE);
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}
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/**
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* @brief Resets AES peripheral
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*
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* @param aes Pointer to the register overlay for the peripheral
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*/
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__STATIC_INLINE void DL_AES_reset(AES_Regs *aes)
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{
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aes->GPRCM.RSTCTL =
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(AES_RSTCTL_KEY_UNLOCK_W | AES_RSTCTL_RESETSTKYCLR_CLR |
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AES_RSTCTL_RESETASSERT_ASSERT);
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}
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/**
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* @brief Returns if AES peripheral was reset
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*
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* @param aes Pointer to the register overlay for the peripheral
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*
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* @return true if peripheral was reset
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* @return false if peripheral wasn't reset
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*
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*/
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__STATIC_INLINE bool DL_AES_isReset(const AES_Regs *aes)
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{
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return ((aes->GPRCM.STAT & AES_STAT_RESETSTKY_MASK) ==
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AES_STAT_RESETSTKY_RESET);
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}
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/**
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* @brief Initializes AES peripheral
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*
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* @param[in] aes Pointer to the register overlay for the
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* peripheral
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*
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* @param[in] aesConfig Configures AES cipher mode, key length and
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* operation configuration. One of @ref DL_AES_MODE
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* @param[in] keyLength Configures AES key length. One of
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* @ref DL_AES_KEY_LENGTH
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*/
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__STATIC_INLINE void DL_AES_init(
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AES_Regs *aes, DL_AES_MODE aesConfig, DL_AES_KEY_LENGTH keyLength)
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{
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DL_Common_updateReg(&aes->AESACTL0,
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((uint32_t) aesConfig | (uint32_t) keyLength),
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(uint32_t)(AES_AESACTL0_OPX_MASK | AES_AESACTL0_CMX_MASK |
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AES_AESACTL0_KLX_MASK));
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}
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/**
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* @brief Immediately resets the complete AES accelerator module even when
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* busy.
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*
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* @param[in] aes Pointer to the register overlay for the
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* peripheral
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*
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*/
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__STATIC_INLINE void DL_AES_softwareReset(AES_Regs *aes)
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{
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aes->AESACTL0 |= (AES_AESACTL0_SWRST_RST);
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}
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/**
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* @brief Returns status of AES error flag
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*
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* @param[in] aes Pointer to the register overlay for the
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* peripheral
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*
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* @return Status of AES module fault flag
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*
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* @retval true flag is set
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* @retval false flag is cleared
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*/
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__STATIC_INLINE bool DL_AES_isFaultFlagSet(const AES_Regs *aes)
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{
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return (
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(aes->AESACTL0 & AES_AESACTL0_ERRFG_MASK) == AES_AESACTL0_ERRFG_ERR);
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}
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/**
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* @brief Clears AES error flag
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*
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* @param[in] aes Pointer to the register overlay for the
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* peripheral
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*
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*/
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__STATIC_INLINE void DL_AES_clearFaultFlag(AES_Regs *aes)
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{
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aes->AESACTL0 &= ~(AES_AESACTL0_ERRFG_ERR);
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}
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/**
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* @brief Enables cipher mode
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*
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* @param[in] aes Pointer to the register overlay for the
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* peripheral
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*
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*/
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__STATIC_INLINE void DL_AES_enableCipherMode(AES_Regs *aes)
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{
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aes->AESACTL0 |= (AES_AESACTL0_CMEN_ENABLE);
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}
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/**
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* @brief Disables cipher mode
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*
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* @param[in] aes Pointer to the register overlay for the
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* peripheral
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*
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*/
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__STATIC_INLINE void DL_AES_disablesCipherMode(AES_Regs *aes)
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{
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aes->AESACTL0 &= ~(AES_AESACTL0_CMEN_ENABLE);
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}
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/**
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* @brief Set cipher block counter value
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*
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* Sets the number of blocks to be encrypted or decrypted, the block counter
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* decrements with each performed encryption or decryption.
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* Block cipher mode must be enabled with @ref DL_AES_enableCipherMode. If block
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* cipher mode is disabled, writes to this register are ignored.
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* If this register has a value > 0 and block cipher mode has been enabled,
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* further writes to this register are ignored until the value of this register
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* is 0.
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*
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* @param aes Pointer to the register overlay for the peripheral
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*
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* @param[in] count The value to set the cipher block counter to.
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* Value between [0x0, 0xFF]
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*
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* @sa DL_AES_enableCipherMode
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*/
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__STATIC_INLINE void DL_AES_setCipherBlockCounter(
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AES_Regs *aes, uint32_t count)
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{
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DL_Common_updateReg(&aes->AESACTL1, count, AES_AESACTL1_BLKCNTX_MASK);
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}
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/**
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* @brief Get current cipher block counter value
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*
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* The block counter decrements with each performed encryption or decryption.
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*
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* @param aes Pointer to the register overlay for the peripheral
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*
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* @return The current cipher block counter value
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*
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* @retval Value between [0x0, 0xFF]
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*/
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__STATIC_INLINE uint32_t DL_AES_getCipherBlockCounter(const AES_Regs *aes)
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{
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return (aes->AESACTL1 & AES_AESACTL1_BLKCNTX_MASK);
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}
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/**
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*
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* @brief Gets the AES module busy status.
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*
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* @param[in] aes Pointer to the register overlay for the
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* peripheral
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* @return Status of AES module
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*
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* @retval true. Module is busy
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* @retval false. Module is in idle state
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*
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*/
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__STATIC_INLINE bool DL_AES_isBusy(const AES_Regs *aes)
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{
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return (
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(aes->AESASTAT & AES_AESASTAT_BUSY_MASK) == AES_AESASTAT_BUSY_BUSY);
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}
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/**
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*
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* @brief Gets the DATAOUT read status
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*
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* @param[in] aes Pointer to the register overlay for the
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* peripheral
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* @return Status of DATAOUT read status
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*
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* @retval true. All bytes read
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* @retval false. Not all bytes read
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*
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*/
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__STATIC_INLINE bool DL_AES_getDataOutReadStatus(const AES_Regs *aes)
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{
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return (
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(aes->AESASTAT & AES_AESASTAT_DOUTRD_MASK) == AES_AESASTAT_DOUTRD_ALL);
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}
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/**
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*
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* @brief Gets Key byte count
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*
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* @param[in] aes Pointer to the register overlay for the
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* peripheral
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*
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* @return Number of Key bytes loaded
|
|
*
|
|
*/
|
|
__STATIC_INLINE uint8_t DL_AES_getKeyBytesCount(const AES_Regs *aes)
|
|
{
|
|
return ((uint8_t)((aes->AESASTAT & AES_AESASTAT_KEYCNTX_MAXNUM) >> 4));
|
|
}
|
|
|
|
/**
|
|
*
|
|
* @brief Gets Data In byte count
|
|
*
|
|
* @param[in] aes Pointer to the register overlay for the
|
|
* peripheral
|
|
*
|
|
* @return Number of Data In bytes loaded
|
|
*
|
|
*/
|
|
__STATIC_INLINE uint8_t DL_AES_getDataInBytesCount(const AES_Regs *aes)
|
|
{
|
|
return ((uint8_t)((aes->AESASTAT & AES_AESASTAT_DINCNTX_MAXNUM) >> 8));
|
|
}
|
|
|
|
/**
|
|
*
|
|
* @brief Gets Data Out byte count
|
|
*
|
|
* @param[in] aes Pointer to the register overlay for the
|
|
* peripheral
|
|
*
|
|
* @return Number of Data Out bytes loaded
|
|
*
|
|
*/
|
|
__STATIC_INLINE uint8_t DL_AES_getDataOutBytesCount(const AES_Regs *aes)
|
|
{
|
|
return ((uint8_t)((aes->AESASTAT & AES_AESASTAT_DOUTCNTX_MAXNUM) >> 12));
|
|
}
|
|
|
|
/**
|
|
*
|
|
* @brief Set bit to write all STATE bytes to STATE registers
|
|
* and triggers a new encryption
|
|
*
|
|
* @param[in] aes Pointer to the register overlay for the
|
|
* peripheral
|
|
*
|
|
*/
|
|
__STATIC_INLINE void DL_AES_setAllDataWritten(AES_Regs *aes)
|
|
{
|
|
aes->AESASTAT |= AES_AESASTAT_DINWR_ALL;
|
|
}
|
|
|
|
/**
|
|
*
|
|
* @brief Set bit to write all KEY bytes to KEY register,
|
|
* which is used to encrypt and decrypt data
|
|
*
|
|
* @param[in] aes Pointer to the register overlay for the
|
|
* peripheral
|
|
*
|
|
*/
|
|
__STATIC_INLINE void DL_AES_setAllKeyWritten(AES_Regs *aes)
|
|
{
|
|
aes->AESASTAT |= AES_AESASTAT_KEYWR_ALL;
|
|
}
|
|
|
|
/**
|
|
*
|
|
* @brief Check if all bytes are to be written to
|
|
* registers containing STATE info
|
|
*
|
|
* @param[in] aes Pointer to the register overlay for the
|
|
* peripheral
|
|
*
|
|
* @retval true All bytes are written to these registers
|
|
* @retval false Not all bytes are written to these registers
|
|
*
|
|
*/
|
|
__STATIC_INLINE bool DL_AES_isAllDataWritten(const AES_Regs *aes)
|
|
{
|
|
return (aes->AESASTAT & AES_AESASTAT_DINWR_MASK) == AES_AESASTAT_DINWR_ALL;
|
|
}
|
|
|
|
/**
|
|
*
|
|
* @brief Check if all bytes are to be written to
|
|
* registers containing KEY info
|
|
*
|
|
* @param[in] aes Pointer to the register overlay for the
|
|
* peripheral
|
|
*
|
|
* @retval true All bytes are written to these registers
|
|
* @retval false Not all bytes are written to these registers
|
|
*/
|
|
__STATIC_INLINE bool DL_AES_isAllKeysWritten(const AES_Regs *aes)
|
|
{
|
|
return (aes->AESASTAT & AES_AESASTAT_KEYWR_MASK) == AES_AESASTAT_KEYWR_ALL;
|
|
}
|
|
|
|
/**
|
|
*
|
|
* @brief Loads a 128 or 256 bit key to AES module.
|
|
*
|
|
* @param[in] aes Pointer to the register overlay for the
|
|
* peripheral
|
|
*
|
|
* @param[in] key Pointer to an aligned uint8_t array that contains
|
|
* the cipher key.
|
|
*
|
|
* @param[in] keyLength length of the key. One of @ref DL_AES_KEY_LENGTH
|
|
*
|
|
* @return Status of operation. Operation will fail if not 32-bit aligned. One
|
|
* of @ref DL_AES_STATUS.
|
|
*
|
|
* @note This function adds additional cycles in order to verify no unaligned
|
|
* access, if this is not necessary, consider using uint32_t pointers and
|
|
* @ref DL_AES_setKeyAligned
|
|
*
|
|
*/
|
|
DL_AES_STATUS DL_AES_setKey(
|
|
AES_Regs *aes, const uint8_t *key, DL_AES_KEY_LENGTH keyLength);
|
|
|
|
/**
|
|
*
|
|
* @brief Loads a 128 or 256 bit key to AES module.
|
|
*
|
|
* @param[in] aes Pointer to the register overlay for the
|
|
* peripheral
|
|
*
|
|
* @param[in] keyAligned Pointer to an uint32_t array that contains the
|
|
* cipher key.
|
|
*
|
|
* @param[in] keyLength length of the key. One of @ref DL_AES_KEY_LENGTH
|
|
*
|
|
* @sa DL_AES_setKey
|
|
*
|
|
*/
|
|
void DL_AES_setKeyAligned(
|
|
AES_Regs *aes, const uint32_t *keyAligned, DL_AES_KEY_LENGTH keyLength);
|
|
|
|
/**
|
|
*
|
|
* @brief XORs an AES 128-bit block of data in software
|
|
*
|
|
* @param[in] data Pointer to initial data block for the operation
|
|
* @param[in] xorData Pointer to 128-bit data block to xor with data
|
|
* @param[out] xorOutputData Pointer to output block of data ^ xorData
|
|
*
|
|
* @return Status of operation. Operation will fail if not 32-bit aligned. One
|
|
* of @ref DL_AES_STATUS.
|
|
*
|
|
* @note This function adds additional cycles in order to verify no unaligned
|
|
* access, if this is not necessary, consider using uint32_t pointers and
|
|
* @ref DL_AES_xorDataAligned
|
|
*
|
|
*/
|
|
DL_AES_STATUS DL_AES_xorData(
|
|
const uint8_t *data, const uint8_t *xorData, uint8_t *xorOutputData);
|
|
|
|
/**
|
|
*
|
|
* @brief XORs an aligned 128-bit data block in software
|
|
*
|
|
* @param[in] dataAligned Pointer to initial data block for the
|
|
* operation
|
|
* @param[in] xorDataAligned Pointer to 128-bit data block to xor with
|
|
* data
|
|
* @param[out] xorOutputDataAligned Pointer to output block of data ^ xorData
|
|
*
|
|
* @sa DL_AES_xorData
|
|
*/
|
|
void DL_AES_xorDataAligned(uint32_t *dataAligned, uint32_t *xorDataAligned,
|
|
uint32_t *xorOutputDataAligned);
|
|
|
|
/**
|
|
*
|
|
* @brief Encrypts a block of data using the AES module.
|
|
*
|
|
* @param[in] aes Pointer to the register overlay for the
|
|
* peripheral
|
|
* @param[in] data Is a pointer to an aligned uint8_t array with a
|
|
* length of 16 that contains data to be encrypted.
|
|
*
|
|
* @return Status of operation. Operation will fail if not 32-bit aligned. One
|
|
* of @ref DL_AES_STATUS.
|
|
*
|
|
* @note This function adds additional cycles in order to verify no unaligned
|
|
* access, if this is not necessary, consider using uint32_t pointers and
|
|
* @ref DL_AES_loadDataInAligned
|
|
*/
|
|
DL_AES_STATUS DL_AES_loadDataIn(AES_Regs *aes, const uint8_t *data);
|
|
|
|
/**
|
|
*
|
|
* @brief Encrypts a block of data using the AES module.
|
|
*
|
|
* @param[in] aes Pointer to the register overlay for the
|
|
* peripheral
|
|
* @param[in] dataAligned Is a pointer to an uint32_t array with a length of
|
|
* 4 that contains data to be encrypted.
|
|
*
|
|
* @sa DL_AES_loadDataIn
|
|
*
|
|
*/
|
|
void DL_AES_loadDataInAligned(AES_Regs *aes, const uint32_t *dataAligned);
|
|
|
|
/**
|
|
*
|
|
* @brief Gets output of encrypted data
|
|
*
|
|
* @param[in] aes Pointer to the register overlay for the
|
|
* peripheral
|
|
* @param[out] data Is a pointer to an uint8_t array with a length of
|
|
* 16 where the output of the AES module will
|
|
* be placed.
|
|
*
|
|
* @return Status of operation. Operation will fail if not 32-bit aligned. One
|
|
* of @ref DL_AES_STATUS.
|
|
*
|
|
* @note This function adds additional cycles in order to verify no unaligned
|
|
* writes, if this is not necessary, consider using uint32_t pointers and
|
|
* @ref DL_AES_getDataOutAligned
|
|
*/
|
|
DL_AES_STATUS DL_AES_getDataOut(const AES_Regs *aes, uint8_t *data);
|
|
|
|
/**
|
|
*
|
|
* @brief Gets output of encrypted data
|
|
*
|
|
* @param[in] aes Pointer to the register overlay for the
|
|
* peripheral
|
|
* @param[in] dataAligned Is a pointer to an uint32_t array with a length of
|
|
* 4 where the output of the AES module will
|
|
* be placed.
|
|
* @sa DL_AES_getDataOut
|
|
*
|
|
*/
|
|
void DL_AES_getDataOutAligned(const AES_Regs *aes, uint32_t *dataAligned);
|
|
|
|
/**
|
|
*
|
|
* @brief Data is XORed with the current word of the state and then block of
|
|
* data is encrypted. Encryption or decryption is started immediately
|
|
* after loading data.
|
|
*
|
|
* @param[in] aes Pointer to the register overlay for the
|
|
* peripheral
|
|
* @param[in] data Is a pointer to an aligned uint8_t array with a
|
|
* length of 16 that contains data to be encrypted.
|
|
*
|
|
* @return Status of operation. Operation will fail if not 32-bit aligned. One
|
|
* of @ref DL_AES_STATUS.
|
|
*
|
|
* @note This function adds additional cycles in order to verify no unaligned
|
|
* access, if this is not necessary, consider using uint32_t pointers and
|
|
* @ref DL_AES_loadXORDataInAligned
|
|
*
|
|
*/
|
|
DL_AES_STATUS DL_AES_loadXORDataIn(AES_Regs *aes, const uint8_t *data);
|
|
|
|
/**
|
|
*
|
|
* @brief Data is XORed with the current word of the state and then block of
|
|
* data is encrypted. Encryption or decryption is started immediately
|
|
* after loading data.
|
|
*
|
|
* @param[in] aes Pointer to the register overlay for the
|
|
* peripheral
|
|
* @param[in] dataAligned Is a pointer to an uint32_t array with a length of
|
|
* 4 that contains data to be encrypted.
|
|
*
|
|
* @sa DL_AES_loadXORDataIn
|
|
*
|
|
*/
|
|
void DL_AES_loadXORDataInAligned(AES_Regs *aes, const uint32_t *dataAligned);
|
|
|
|
/**
|
|
*
|
|
* @brief Data is XORed with the current word of the state and then block of
|
|
* data is encrypted. Encryption or decryption is NOT started after
|
|
* loading data.
|
|
*
|
|
* @param[in] aes Pointer to the register overlay for the
|
|
* peripheral
|
|
* @param[in] data Is a pointer to an aligned uint8_t array with a
|
|
* length of 16 that contains data to be encrypted.
|
|
*
|
|
* @return Status of operation. Operation will fail if not 32-bit aligned. One
|
|
* of @ref DL_AES_STATUS.
|
|
*
|
|
* @note This function adds additional cycles in order to verify no unaligned
|
|
* access, if this is not necessary, consider using uint32_t pointers and
|
|
* @ref DL_AES_loadXORDataInWithoutTriggerAligned
|
|
*
|
|
*/
|
|
DL_AES_STATUS DL_AES_loadXORDataInWithoutTrigger(
|
|
AES_Regs *aes, const uint8_t *data);
|
|
|
|
/**
|
|
*
|
|
* @brief Data is XORed with the current word of the state and then block of
|
|
* data is encrypted. Encryption or decryption is NOT started after
|
|
* loading data.
|
|
*
|
|
* @param[in] aes Pointer to the register overlay for the
|
|
* peripheral
|
|
* @param[in] dataAligned Is a pointer to an uint32_t array with a length of
|
|
* 4 that contains data to be encrypted.
|
|
*
|
|
* @sa DL_AES_loadXORDataInWithoutTrigger
|
|
*
|
|
*/
|
|
void DL_AES_loadXORDataInWithoutTriggerAligned(
|
|
AES_Regs *aes, const uint32_t *dataAligned);
|
|
|
|
/**
|
|
* @brief Enable AES Ready interrupt
|
|
*
|
|
* @param[in] aes Pointer to the register overlay for the
|
|
* peripheral
|
|
*/
|
|
__STATIC_INLINE void DL_AES_enableInterrupt(AES_Regs *aes)
|
|
{
|
|
aes->CPU_INT.IMASK |= DL_AES_INTERRUPT_AES_READY;
|
|
}
|
|
|
|
/**
|
|
* @brief Enables DMA trigger 0 to publish AES events to the DMA
|
|
*
|
|
* @param[in] aes Pointer to the register overlay for the
|
|
* peripheral
|
|
*/
|
|
__STATIC_INLINE void DL_AES_enableDMATrigger0Interrupt(AES_Regs *aes)
|
|
{
|
|
aes->DMA_TRIG0.IMASK |= DL_AES_EVENT_AES_DMA_TRIGGER0;
|
|
}
|
|
|
|
/**
|
|
* @brief Enables DMA trigger 1 to publish AES events to the DMA
|
|
*
|
|
* @param[in] aes Pointer to the register overlay for the
|
|
* peripheral
|
|
*/
|
|
__STATIC_INLINE void DL_AES_enableDMATrigger1Interrupt(AES_Regs *aes)
|
|
{
|
|
aes->DMA_TRIG1.IMASK |= DL_AES_EVENT_AES_DMA_TRIGGER1;
|
|
}
|
|
|
|
/**
|
|
* @brief Enables DMA trigger 2 to publish AES events to the DMA
|
|
*
|
|
* @param[in] aes Pointer to the register overlay for the
|
|
* peripheral
|
|
*/
|
|
__STATIC_INLINE void DL_AES_enableDMATrigger2Interrupt(AES_Regs *aes)
|
|
{
|
|
aes->DMA_TRIG2.IMASK |= DL_AES_EVENT_AES_DMA_TRIGGER2;
|
|
}
|
|
|
|
/**
|
|
* @brief Disable AES Ready interrupt
|
|
*
|
|
* @param[in] aes Pointer to the register overlay for the
|
|
* peripheral
|
|
*/
|
|
__STATIC_INLINE void DL_AES_disableInterrupt(AES_Regs *aes)
|
|
{
|
|
aes->CPU_INT.IMASK &= ~(AES_CPU_INT_IMASK_AESRDY_MASK);
|
|
}
|
|
|
|
/**
|
|
* @brief Disable DMA Trigger 0 Event
|
|
*
|
|
* @param[in] aes Pointer to the register overlay for the
|
|
* peripheral
|
|
*/
|
|
__STATIC_INLINE void DL_AES_disableDMATrigger0Event(AES_Regs *aes)
|
|
{
|
|
aes->DMA_TRIG0.IMASK &= ~(AES_DMA_TRIG0_IMASK_DMA0_MASK);
|
|
}
|
|
|
|
/**
|
|
* @brief Disable DMA Trigger 1 Event
|
|
*
|
|
* @param[in] aes Pointer to the register overlay for the
|
|
* peripheral
|
|
*/
|
|
__STATIC_INLINE void DL_AES_disableDMATrigger1Event(AES_Regs *aes)
|
|
{
|
|
aes->DMA_TRIG1.IMASK &= ~(AES_DMA_TRIG1_IMASK_DMA1_MASK);
|
|
}
|
|
|
|
/**
|
|
* @brief Disable DMA Trigger 2 Event
|
|
*
|
|
* @param[in] aes Pointer to the register overlay for the
|
|
* peripheral
|
|
*/
|
|
__STATIC_INLINE void DL_AES_disableDMATrigger2Event(AES_Regs *aes)
|
|
{
|
|
aes->DMA_TRIG2.IMASK &= ~(AES_DMA_TRIG2_IMASK_DMA2_MASK);
|
|
}
|
|
|
|
/**
|
|
* @brief Check if AES Ready interrupt is enabled
|
|
*
|
|
* @param[in] aes Pointer to the register overlay for the
|
|
* peripheral
|
|
*
|
|
* @return If AES Ready interrupt is enabled
|
|
*
|
|
* @retval DL_AES_INTERRUPT_AES_READY if AES Ready interrupt is enabled
|
|
* @retval 0 if AES Ready interrupt is not enabled
|
|
*/
|
|
__STATIC_INLINE uint32_t DL_AES_getEnabledInterrupts(const AES_Regs *aes)
|
|
{
|
|
return (aes->CPU_INT.IMASK & AES_CPU_INT_IMASK_AESRDY_MASK);
|
|
}
|
|
|
|
/**
|
|
* @brief Check if DMA Trigger 0 Event is enabled
|
|
*
|
|
* @param[in] aes Pointer to the register overlay for the
|
|
* peripheral
|
|
*
|
|
* @return If DMA Trigger 0 Event is enabled
|
|
*
|
|
* @retval DL_AES_EVENT_AES_DMA_TRIGGER0 if DMA Trigger 0 Event is enabled
|
|
* @retval 0 if DMA Trigger 0 Event is not enabled
|
|
*/
|
|
__STATIC_INLINE uint32_t DL_AES_getEnabledDMATrigger0Event(const AES_Regs *aes)
|
|
{
|
|
return (aes->DMA_TRIG0.IMASK & AES_DMA_TRIG0_IMASK_DMA0_MASK);
|
|
}
|
|
|
|
/**
|
|
* @brief Check if DMA Trigger 1 Event is enabled
|
|
*
|
|
* @param[in] aes Pointer to the register overlay for the
|
|
* peripheral
|
|
*
|
|
* @return If DMA Trigger 1 Event is enabled
|
|
*
|
|
* @retval DL_AES_EVENT_AES_DMA_TRIGGER1 if DMA Trigger 1 Event is enabled
|
|
* @retval 0 if DMA Trigger 1 Event is not enabled
|
|
*/
|
|
__STATIC_INLINE uint32_t DL_AES_getEnabledDMATrigger1Event(const AES_Regs *aes)
|
|
{
|
|
return (aes->DMA_TRIG1.IMASK & AES_DMA_TRIG1_IMASK_DMA1_MASK);
|
|
}
|
|
|
|
/**
|
|
* @brief Check if DMA Trigger 2 Event is enabled
|
|
*
|
|
* @param[in] aes Pointer to the register overlay for the
|
|
* peripheral
|
|
*
|
|
* @return If DMA Trigger 2 Event is enabled
|
|
*
|
|
* @retval DL_AES_EVENT_AES_DMA_TRIGGER2 if DMA Trigger 2 Event is enabled
|
|
* @retval 0 if DMA Trigger 2 Event is not enabled
|
|
*/
|
|
__STATIC_INLINE uint32_t DL_AES_getEnabledDMATrigger2Event(const AES_Regs *aes)
|
|
{
|
|
return (aes->DMA_TRIG2.IMASK & AES_DMA_TRIG2_IMASK_DMA2_MASK);
|
|
}
|
|
|
|
/**
|
|
* @brief Check interrupt flag of AES Ready interrupt
|
|
*
|
|
* Checks if AES Ready interrupt that was previously enabled is pending.
|
|
*
|
|
* @param[in] aes Pointer to the register overlay for the
|
|
* peripheral
|
|
*
|
|
* @return If AES Ready interrupt is pending
|
|
*
|
|
* @retval DL_AES_INTERRUPT_AES_READY if AES Ready interrupt is pending
|
|
* @retval 0 if AES Ready interrupt is not pending
|
|
*
|
|
* @sa DL_AES_enableInterrupt
|
|
*/
|
|
__STATIC_INLINE uint32_t DL_AES_getEnabledInterruptStatus(const AES_Regs *aes)
|
|
{
|
|
return (aes->CPU_INT.MIS & AES_CPU_INT_IMASK_AESRDY_MASK);
|
|
}
|
|
|
|
/**
|
|
* @brief Check interrupt flag of DMA Trigger 0 Event
|
|
*
|
|
* Checks if DMA Trigger 0 Event that was previously enabled is pending.
|
|
*
|
|
* @param[in] aes Pointer to the register overlay for the
|
|
* peripheral
|
|
*
|
|
* @return If DMA Trigger 0 Event is pending
|
|
*
|
|
* @retval DL_AES_EVENT_AES_DMA_TRIGGER0 if DMA Trigger 0 Event is pending
|
|
* @retval 0 if DMA Trigger 0 Event is not pending
|
|
*
|
|
* @sa DL_AES_enableDMATrigger0Event
|
|
*/
|
|
__STATIC_INLINE uint32_t DL_AES_getEnabledDMATrigger0EventStatus(
|
|
const AES_Regs *aes)
|
|
{
|
|
return (aes->DMA_TRIG0.MIS & AES_DMA_TRIG0_IMASK_DMA0_MASK);
|
|
}
|
|
|
|
/**
|
|
* @brief Check interrupt flag of DMA Trigger 1 Event
|
|
*
|
|
* Checks if DMA Trigger 1 Event that was previously enabled is pending.
|
|
*
|
|
* @param[in] aes Pointer to the register overlay for the
|
|
* peripheral
|
|
*
|
|
* @return If DMA Trigger 1 Event is pending
|
|
*
|
|
* @retval DL_AES_EVENT_AES_DMA_TRIGGER1 if DMA Trigger 1 Event is pending
|
|
* @retval 0 if DMA Trigger 1 Event is not pending
|
|
*
|
|
* @sa DL_AES_enableDMATrigger1Event
|
|
*/
|
|
__STATIC_INLINE uint32_t DL_AES_getEnabledDMATrigger1EventStatus(
|
|
const AES_Regs *aes)
|
|
{
|
|
return (aes->DMA_TRIG1.MIS & AES_DMA_TRIG1_IMASK_DMA1_MASK);
|
|
}
|
|
|
|
/**
|
|
* @brief Check interrupt flag of DMA Trigger 2 Event
|
|
*
|
|
* Checks if DMA Trigger 2 Event that was previously enabled is pending.
|
|
*
|
|
* @param[in] aes Pointer to the register overlay for the
|
|
* peripheral
|
|
*
|
|
* @return If DMA Trigger 2 Event is pending
|
|
*
|
|
* @retval DL_AES_EVENT_AES_DMA_TRIGGER2 if DMA Trigger 2 Event is pending
|
|
* @retval 0 if DMA Trigger 2 Event is not pending
|
|
*
|
|
* @sa DL_AES_enableDMATrigger2Event
|
|
*/
|
|
__STATIC_INLINE uint32_t DL_AES_getEnabledDMATrigger2EventStatus(
|
|
const AES_Regs *aes)
|
|
{
|
|
return (aes->DMA_TRIG2.MIS & AES_DMA_TRIG2_IMASK_DMA2_MASK);
|
|
}
|
|
|
|
/**
|
|
* @brief Check interrupt flag of AES Ready interrupt
|
|
*
|
|
* Checks if AES Ready Interrupt is pending. Interrupt does not have to
|
|
* be previously enabled.
|
|
*
|
|
* @param[in] aes Pointer to the register overlay for the
|
|
* peripheral
|
|
*
|
|
* @return If AES Ready interrupt is pending
|
|
*
|
|
* @retval DL_AES_EVENT_AES_DMA_TRIGGER0 if AES Ready interrupt is pending
|
|
* @retval 0 if AES Ready interrupt is not pending
|
|
*/
|
|
__STATIC_INLINE uint32_t DL_AES_getRawInterruptStatus(const AES_Regs *aes)
|
|
{
|
|
return (aes->CPU_INT.RIS & AES_CPU_INT_IMASK_AESRDY_MASK);
|
|
}
|
|
|
|
/**
|
|
* @brief Check interrupt flag of DMA Trigger 0 Event
|
|
*
|
|
* Checks if DMA Trigger 0 Event is pending. Event does not have to
|
|
* be previously enabled.
|
|
*
|
|
* @param[in] aes Pointer to the register overlay for the
|
|
* peripheral
|
|
*
|
|
* @return If DMA Trigger 0 Event is pending
|
|
*
|
|
* @retval DL_AES_EVENT_AES_DMA_TRIGGER0 if DMA Trigger 0 Event is pending
|
|
* @retval 0 if DMA Trigger 0 Event is not pending
|
|
*/
|
|
__STATIC_INLINE uint32_t DL_AES_getRawDMATrigger0EventStatus(
|
|
const AES_Regs *aes)
|
|
{
|
|
return (aes->DMA_TRIG0.RIS & AES_DMA_TRIG0_IMASK_DMA0_MASK);
|
|
}
|
|
|
|
/**
|
|
* @brief Check interrupt flag of DMA Trigger 1 Event
|
|
*
|
|
* Checks if DMA Trigger 1 Event is pending. Event does not have to
|
|
* be previously enabled.
|
|
*
|
|
* @param[in] aes Pointer to the register overlay for the
|
|
* peripheral
|
|
*
|
|
* @return If DMA Trigger 1 Event is pending
|
|
*
|
|
* @retval DL_AES_EVENT_AES_DMA_TRIGGER0 if DMA Trigger 1 Event is pending
|
|
* @retval 0 if DMA Trigger 1 Event is not pending
|
|
*/
|
|
__STATIC_INLINE uint32_t DL_AES_getRawDMATrigger1EventStatus(
|
|
const AES_Regs *aes)
|
|
{
|
|
return (aes->DMA_TRIG1.RIS & AES_DMA_TRIG1_IMASK_DMA1_MASK);
|
|
}
|
|
|
|
/**
|
|
* @brief Check interrupt flag of DMA Trigger 2 Event
|
|
*
|
|
* Checks if DMA Trigger 2 Event is pending. Event does not have to
|
|
* be previously enabled.
|
|
*
|
|
* @param[in] aes Pointer to the register overlay for the
|
|
* peripheral
|
|
*
|
|
* @return If DMA Trigger 2 Event is pending
|
|
*
|
|
* @retval DL_AES_EVENT_AES_DMA_TRIGGER0 if DMA Trigger 2 Event is pending
|
|
* @retval 0 if DMA Trigger 2 Event is not pending
|
|
*/
|
|
__STATIC_INLINE uint32_t DL_AES_getRawDMATrigger2EventStatus(
|
|
const AES_Regs *aes)
|
|
{
|
|
return (aes->DMA_TRIG2.RIS & AES_DMA_TRIG2_IMASK_DMA2_MASK);
|
|
}
|
|
|
|
/**
|
|
* @brief Get highest priority pending AES interrupt
|
|
*
|
|
* Checks if AES Ready Interrupt is pending. Interrupt does not have to
|
|
* be previously enabled.
|
|
*
|
|
* @param[in] aes Pointer to the register overlay for the
|
|
* peripheral
|
|
*
|
|
* @return The highest priority pending AES interrupt
|
|
*/
|
|
__STATIC_INLINE DL_AES_IIDX DL_AES_getPendingInterrupt(const AES_Regs *aes)
|
|
{
|
|
uint32_t interruptIdx = (uint32_t) aes->CPU_INT.IIDX;
|
|
|
|
return (DL_AES_IIDX) interruptIdx;
|
|
}
|
|
|
|
/**
|
|
* @brief Get highest priority pending DMA Trigger 0 Event
|
|
*
|
|
* Checks if DMA Trigger 0 Event os pending. Event does not have to
|
|
* be previously enabled.
|
|
*
|
|
* @param[in] aes Pointer to the register overlay for the
|
|
* peripheral
|
|
*
|
|
* @return The highest priority pending DMA Trigger 0 Event
|
|
*/
|
|
__STATIC_INLINE DL_AES_IIDX DL_AES_getPendingDMATrigger0Event(
|
|
const AES_Regs *aes)
|
|
{
|
|
uint32_t eventIdx = (uint32_t) aes->DMA_TRIG0.IIDX;
|
|
|
|
return (DL_AES_IIDX) eventIdx;
|
|
}
|
|
|
|
/**
|
|
* @brief Get highest priority pending DMA Trigger 1 Event
|
|
*
|
|
* Checks if DMA Trigger 1 Event os pending. Event does not have to
|
|
* be previously enabled.
|
|
*
|
|
* @param[in] aes Pointer to the register overlay for the
|
|
* peripheral
|
|
*
|
|
* @return The highest priority pending DMA Trigger 1 Event
|
|
*/
|
|
__STATIC_INLINE DL_AES_IIDX DL_AES_getPendingDMATrigger1Event(
|
|
const AES_Regs *aes)
|
|
{
|
|
uint32_t eventIdx = (uint32_t) aes->DMA_TRIG1.IIDX;
|
|
|
|
return (DL_AES_IIDX) eventIdx;
|
|
}
|
|
|
|
/**
|
|
* @brief Get highest priority pending DMA Trigger 2 Event
|
|
*
|
|
* Checks if DMA Trigger 2 Event os pending. Event does not have to
|
|
* be previously enabled.
|
|
*
|
|
* @param[in] aes Pointer to the register overlay for the
|
|
* peripheral
|
|
*
|
|
* @return The highest priority pending DMA Trigger 2 Event
|
|
*/
|
|
__STATIC_INLINE DL_AES_IIDX DL_AES_getPendingDMATrigger2Event(
|
|
const AES_Regs *aes)
|
|
{
|
|
uint32_t eventIdx = (uint32_t) aes->DMA_TRIG2.IIDX;
|
|
|
|
return (DL_AES_IIDX) eventIdx;
|
|
}
|
|
|
|
/**
|
|
* @brief Clear pending AES Ready Interrupt
|
|
*
|
|
* @param[in] aes Pointer to the register overlay for the
|
|
* peripheral
|
|
*/
|
|
__STATIC_INLINE void DL_AES_clearInterruptStatus(AES_Regs *aes)
|
|
{
|
|
aes->CPU_INT.ICLR |= AES_CPU_INT_IMASK_AESRDY_MASK;
|
|
}
|
|
|
|
/**
|
|
* @brief Clear pending DMA Trigger 0 Event
|
|
*
|
|
* @param[in] aes Pointer to the register overlay for the
|
|
* peripheral
|
|
*/
|
|
__STATIC_INLINE void DL_AES_clearDMATrigger0EventStatus(AES_Regs *aes)
|
|
{
|
|
aes->DMA_TRIG0.ICLR |= AES_DMA_TRIG0_IMASK_DMA0_MASK;
|
|
}
|
|
|
|
/**
|
|
* @brief Clear pending DMA Trigger 1 Event
|
|
*
|
|
* @param[in] aes Pointer to the register overlay for the
|
|
* peripheral
|
|
*/
|
|
__STATIC_INLINE void DL_AES_clearDMATrigger1EventStatus(AES_Regs *aes)
|
|
{
|
|
aes->DMA_TRIG1.ICLR |= AES_DMA_TRIG1_IMASK_DMA1_MASK;
|
|
}
|
|
|
|
/**
|
|
* @brief Clear pending DMA Trigger 2 Event
|
|
*
|
|
* @param[in] aes Pointer to the register overlay for the
|
|
* peripheral
|
|
*/
|
|
__STATIC_INLINE void DL_AES_clearDMATrigger2EventStatus(AES_Regs *aes)
|
|
{
|
|
aes->DMA_TRIG2.ICLR |= AES_DMA_TRIG2_IMASK_DMA2_MASK;
|
|
}
|
|
|
|
/**
|
|
* @brief Save AES configuration before entering a power loss state.
|
|
* Note that operation-specific variables (intermediate data,
|
|
* key, IV) will need to be re-loaded after picking up the
|
|
* peripheral from a powerloss state.
|
|
*
|
|
* @param[in] aes Pointer to the register overlay for the peripheral
|
|
*
|
|
* @param[in] ptr Configuration backup setup structure. See
|
|
* @ref DL_AES_backupConfig.
|
|
*
|
|
* @retval FALSE if a configuration already exists in ptr (will not be
|
|
* overwritten). TRUE if a configuration was successfully saved
|
|
*
|
|
*/
|
|
bool DL_AES_saveConfiguration(const AES_Regs *aes, DL_AES_backupConfig *ptr);
|
|
|
|
/**
|
|
* @brief Restore AES configuration after leaving a power loss state.
|
|
* Note that operation-specific variables (intermediate data,
|
|
* key, IV) will need to be re-loaded after picking up the
|
|
* peripheral from a powerloss state.
|
|
*
|
|
* @param[in] aes Pointer to the register overlay for the peripheral
|
|
*
|
|
* @param[in] ptr Configuration backup setup structure. See
|
|
* @ref DL_AES_backupConfig.
|
|
*
|
|
* @retval FALSE if a configuration does not exist in ptr (will not be
|
|
* loaded). TRUE if a configuration successfully loaded
|
|
*
|
|
*/
|
|
bool DL_AES_restoreConfiguration(AES_Regs *aes, DL_AES_backupConfig *ptr);
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#endif /* __MSPM0_HAS_AES__ */
|
|
|
|
#endif /* ti_dl_dl_aes__include */
|
|
/** @}*/
|